The invention relates to a digital data register with a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal, an output driver with a data output providing a digital data output signal for application to an associated memory module, and a flip-flop arranged between the data input and the data output. A preferred application of the data register is the use in a memory system operating at clock frequencies as high as 800 MHz and above.
The purpose of such a data register, also referred to as a “registered data buffer,” is to ensure the correct setup and hold timing for the related memory modules. The register should also have a phase jitter cleaning function for the clock used in the memory system. Both requirements can be met in a straightforward approach with a data register wherein a flip-flop is inserted in each data path and all flip-flops are clocked with a clean clock provided by a phase locked loop (PLL). By adjusting the delay time of a delay element in the clock input path in relation to the propagation delay time (tpd) of the data input path upstream of the flip-flop the appropriate setup and hold timing can be achieved on the pre-register side. On the post-register side, a delay element is inserted in the clock output path so as to move the clock edge to the center of the data eye of the register's data output signal. The clock output driver must be matched with the data output drivers to ensure stable timing conditions on the post-register side over variations of process, supply voltage and temperature (PVT). Likewise, the clock input path should be matched with the data input paths on the pre-register side. In this context, “matched” means similar semiconductor structures on the die so that variations of semiconductor process, supply voltage and temperature have the same effect on the propagation times of matched structures.
The pre-register timing is, however, linked with the post-register timing by the propagation delay time (tpd) from the clock input to the data output. This propagation delay should be small and constant over PVT variations. It is not possible to achieve a PVT invariant propagation delay with the architecture considered above.